YunSDR

1. YunSDR Y550


y5501   y5502

Y550 is the high end SDR development platform designed with largest Xilinx ZYNQ device XC7Z100 that can accommodate high performance MIMO communication design that requires heavy computation power. Y550 is equipped with 4 TX and 4 RX channels and cascade-able to realize MIMO systems.

Y550 front end is powered by 2X AD9371 transceivers, each channel can provide up to 100MHz channel frequency BW. Y550’s clock system is flexible, supports external PPS, clock reference and GPS synchronizations that are needed for high performance MIMO design. Multiple Y550 can be cascaded to form 128 x 128 Massive MIMO system.

Technical Specifications

RF Channels

4 x TX, 4 x RX

RX/TX Band

300MHz to 6GHz

Channel BW

TX: 250MHz ; RX: 100MHz

RF Power

10 dBm, All Channels @ 0.3 to 6GHz

RF Tolerance

+/- 1ppm

EVM

<-38dB LTE 20MHz downlink @ 2600MHz BW

Synchronizer Port

Support 1 PPS, external 10MHz input

ADC

16bits 122.88MS/s, 125MS/s or 153.6MS/s

DAC

14 bits @ 122.88MS/s, 125MS/s or 153.6MS/s

SOC Specifications

Xilinx ZYNQ XC7Z100, Dual core Cortex A9@ 1.5GHz

Memories

1 GBytes DDR3 for PS, 1 GBytes DDR3 for PL

Data Ports

Gigabits Ethernet, USB 3.0 OTG, USB UART

Optical Interface

4 x SFP+ ports

Synchronization ports

External Reference IN/OUT

 

2. YunSDR 320

yunsdr  Y320 SMALL

 

Y320 development platform is designed to support RF communication, GPS navigation system & Spectrum security research. The adaptive platform based on Xilinx ZYNQ SOC makes it a great candidate for real time communications system PHY and MAC layer design and development.

Software EcoSystem for Y320 includes MATLAB Simulink, NI Labview and GNURadio/Python. Example applications include real-time HD graphic wireless transmission for UAV, SDR and private network radio communications endpoints. Y320 supports external reference clock input and 1Pulse Per Second (PPS) synchronizer, if equipped together with YunGCD-10 (Clock distributions), Y320 can be a good candidate for Massive MIMO development platform.

y3201   y320 2

Technical Specifications

RF Channels

2 x TX, 2 x RX

RX/TX Band

70MHz to 6GHz

Channel BW

200kHZ to 56MHz

RF Power

15 dBm, Single Channel @ 20MHz

RF Tolerance

+/- 1ppm

EVM

<3% @ 5dBm, 20MHz BW

Synchronizer Port

Support 1 pps, external 10MHz reference input

ADC

Dual channels 12 bits @ 61.44MSPS

DAC

Dual channels 12 bits @ 61.44MSPS

SOC Specifications

Xilinx ZYNQ XC7Z020, Dual Core Cortex A9

Memories

512 MBytes DDR3

Data Ports

Gigabits Ethernet, USB 3.0 OTG, USB UART

Display Interface

Display Port with 4k support

Storage

M2 SSD/SATA 3.0

3.  YunSDR Y300

y300

Y300 is specially crafted version of Y320 for engineering education purpose. The SDR platform comes with MATLAB based labs support materials for undergraduates and master’s degree engineering labs. Y300 education kits provide hands on experience for university students who are studying [Signal & Systems] & [Digital Communications]

MATLAB Basic Labs include:

  • Single tone signal generation and transmission
  • ASK - Amplitude Shift Keying modulation
  • MASK – Multiple Amplitude Shift Keying modulation
  • FSK – Frequency Shift Keying
  • PSK – Phase Shift Keying
  • QAM
  • Single-Carrier Frequency Domain Equalization

MATLAB Advance Labs include:

  • OFDM baseband transmitter /receiver
  • OFDM baseband receiver carrier frequency synchronizer
  • OFDM baseband receiver channel estimation
  • MIMO OFDM baseband transmitter / receiver

 Technical Specifications

RF Channels

2 x TX, 2 x RX

RX/TX Band

70MHz to 6GHz

Channel BW

200kHZ to 56MHz

RF Power

5 dBm, Single Channel @ 20MHz

RF Tolerance

+/- 1ppm

EVM

<3% @ 5dBm, 20MHz BW

ADC

Dual channels 12 bits @ 61.44MSPS

DAC

Dual channels 12 bits @ 61.44MSPS

SOC Specifications

Xilinx ZYNQ XC7Z020, Dual Core Cortex A9

Memories

512 MBytes DDR3

Data Ports

USB 2.0, FPGA JTAG

 

 

 

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