FPGA Implementation with SIMULINK and System Generator

Course Description
This is a three-day training class that provides system architects, DSP designers, and FPGA designers a hands-on course covering how to develop signal processing algorithm for FPGA device using Simulink and the Xilinx design flow for implementing DSP functions using System Generator.

Duration
3 Days

Prerequisites

Attended "Comprehensive MATLAB" and "Comprehensive SIMULINK", or equivalent experience using MATLAB & SIMULINK. Participants are expected to have some exposure to signal processing techniques prior to taking this course.

In addition, you are to have the knowledge of Xilinx FPGA fundamentals.

Although the course includes some very basic revision of some DSP algorithms, it is expected that you understand the basics of digital signal processing theory for functions such as:

  • FIR (Finite Impulse Response)
  • Oscillators and Mixers
  • FFT (Fast Fourier Transform) algorithm and equalizer

Why this training pays huge dividends

After completing this training, you will be able to:

  • Use Simulink to perform system-level DSP design
  • Approach the complexities of high-performance DSP design
  • Implement a design from algorithm concept to hardware verification using Xilinx automatic translation (System Generator) and implementation (ISE) tool

Course Outline

Day 1
SIMULINK for Signal Processing
This provides an introduction on how to develop signal processing algorithms for FPGA device using Simulink. The basics of using the Signal Processing Blockset in SIMULINK to analyze and design a signal processing system will be covered. The first part includes an introduction to signal processing with a concentration on representations of signals in MATLAB, signal analysis, and filter design, with FIR design. Multirate system is also discussed. 

Simulink Interface
Objective: This section introduces the Simulink interface and teaches basic concepts that will help new users to get comfortable with the environment.

  • Simulink Library Browser
  • Setting up a model
  • Add and Connect blocks
  • Input from MATLAB workspace
  • Model callbacks
  • Processing vectors and matrices
  • Exploring the time scope
  • Exploring the spectrum scope
  • Initializing parameters and defining data


Signal Analysis
Objective: This section uses a signal processing system to discuss important Simulink concepts such as multichannel frame-based systems, simulation from the command line, and defining system I/O. Following this section, students should be comfortable with how Simulink propagates signals and data during a simulation.

  • Analyzing a signal
  • Building an algorithm
  • Frame-based processing
  • Simulating models from the command line
  • Multichannel signals
  • Buffering
  • Introducing noise
  • Defining the system I/O using the Import block

Filter
Objective: This section introduces the various tools and components that help users design filters in Simulink. We introduce these filter components and apply them on various noisy signals.

  • Filtering library
  • Digital filter block
  • Filter architectures
  • Digital filter design block and FDATool
  • Filter realization wizard
  • Filter Design Toolbox library

Multirate Systems
Objective: This section discusses the concept of multirate systems. A basic multirate model is used to illustrate multirate modeling features in Simulink. The section finishes with a case study of a digital audio rate converter.

  • Multirate systems
  • Discrete solvers
  • Resampling
  • Creating subsystems
  • Aliasing and anti-aliasing filter
  • Case study: digital audio rate converter


Day 2 & 3

DSP Design using System Generator
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost Digital Signal Processing designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

• Introduction to System Generator
• Simulink Software Basics
Lab 1: Using the Simulink Software
• Basic Xilinx Design Capture
Lab 2: Getting Started with Xilinx System Generator
• Signal Routing
Lab 3: Signal Routing
• Implementing System Control
Lab 4: Implementing System Control
• Multi-Rate Systems
Lab 5: Designing a MAC-based FIR
• Filter Design
Lab 6: Designing a FIR Filter Using the FIR Compiler Block
• System Generator, Vivado Design Suite, Project Navigator, and XPS Integration
Lab 7: System Generator and Vivado IDE Integration
• Kintex-7 FPGA DSP Platforms
Lab 8a: System Generator and Vivado HLS Tool Integration
Lab 8b: AXI-4 Lite Interface Synthesis


Lab Descriptions

Lab 1: Using the Simulink Software – Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.
Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
Lab 3: Signal Routing - Design padding and unpadding logic by using signal routing blocks.
Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.
Lab 5: Designing a MAC-based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.
Lab 6: Designing a FIR Filter Using the FIR Compiler Block or DAFIR Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
Lab 7: System Generator and Vivado IDE Integration – Embed System Generator models into the Vivado IDE.
Lab 8a: System Generator and Vivado HLS Tool Integration – Generate IP from a C-based design to use with System Generator.
Lab 8b: AXI4-Lite Interface Synthesis – Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.

 

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