How to Design a High-Speed Memory Interface

This course teaches hardware designers who are new to high-speed memory I/O to design a memory interface in Xilinx FPGAs. It introduces designers to the basic concepts of high-speed memory I/O design, implementation, and debugging using 7 series FPGAs. 

Additionally, students will learn about the tools available for high-speed memory interface design, debug, and implementation of high-speed memory interfaces.

The major memory types covered are DDR2 and DDR3. The following memory types are covered on demand: RLDRAMII, LPDDR2, and QDRII+. Labs are available for DDR3 on the Kintex®-7 FPGA KC705 board.

Level

Connectivity 3 

Training Duration

2 days

Who Should Attend?

  • FPGA designers and logic designers

Prerequisites

  • VHDL or Verilog experience or Designing with VHDL or Designing with Verilog course
  • Familiarity with logic design: state machines and synchronous design
  • Very helpful to have: 
    • Basic knowledge of FPGA architecture 
    • Familiarity with Xilinx implementation tools 
  • Nice to have: 
    • Familiarity with I/O basics 
    • Familiarity with high-speed I/O standard

Software Tools

  • Vivado® Design or System Edition 2015.1
  • Mentor Graphics QuestaSim Advanced Simulator 10.3d
  • Mentor Graphics HyperLynx SI 9.x

Hardware 

  • Architecture: 7 series FPGAs*
  • Demo board: Kintex-7 FPGA KC705 board*

 

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify the FPGA resources required for memory interfaces
  • Describe different types of memories
  • Utilize Xilinx tools to generate memory interface designs 
  • Simulate memory interfaces with the Xilinx Vivado simulator
  • Implement memory interfaces
  • Identify the board design options for the realization of memory interfaces
  • Test and debug your memory interface design
  • Run basic memory interface signal integrity simulations

Course Outline

 

Day 1

1.1 Course Introduction

 

1.2 7 Series FPGAs Overview

 

1.3 Memory Devices Overview

 

1.4 7 Series Memory Interface Resources

 

1.5 Memory Controller Details and Signals

 

1.6 MIG Design Generation

 

1.7 Lab 1: MIG Core Generation

Create a DDR3 memory controller using the Memory Interface Generator (MIG) in the Vivado IP catalog. Customize the soft core memory controller for the board.

1.8 MIG Design Simulation

 

1.9 Lab 2: MIG Design Simulation

Simulate the memory controller created in Lab 1 using the Vivado simulator or Mentor Graphics QuestaSim simulator.

 

Day 2

2.1 MIG Design Implementation

 

2.2 Lab 3: MIG Design Implementation

Implement the memory controller created in the previous labs. Modify constraints, synthesize, implement, create the bitstream, program the FPGA, and check the functionality.

 

2.3 Memory Interface Test and Debugging

 

2.4 Lab 4: MIG Design Debugging

Debug the memory interface design utilizing the Vivado logic analzyer.

 

2.5 MIG in Embedded Designs

 

2.6 Lab 5: MIG in IP Integrator

Use the block design editor to include the MIG IP in a given processor design.

2.7 Memory Interface Board-Level Design

2.8 DDR3 PCB Simulation (optional)

 

2.9 Lab 6: DDR3 Signal Integrity Simulation (optional)

Learn basic signal analysis options to check waveforms and design optimization.

 

DOWNLOAD REGISTRATION FORM

 

  ONLINE REGISTRATION

 

 

 

Course Registration Form


Course Title
Invalid Input

or Key in Your Own Title
Invalid Input

Course Start Date

Invalid Input

Sponsorship (*)
Invalid Input


Contact Person


Salutation(*)
Invalid Input

Name(*)
Invalid Input

Designation/ Department/ Division(*)
Invalid Input

Company(*)
Invalid Input

Billing Address (*)
Invalid Input

Street Address

(*)
Invalid Input

Street Address Line 2

City(*)
Invalid Input

State / Province(*)
Invalid Input

Postal / Zip Code(*)
Invalid Input

Telephone(*)
Invalid Input

Fax
Invalid Input

Email Address (*)
Invalid Input


Participant Details


Participant Salution 1
Invalid Input

Participant Name1
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 2
Invalid Input

Participant Name2
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 3
Invalid Input

Participant Name 3
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Payment Method(*)
Invalid Input

Cheque number
Invalid Input

PO Number
Invalid Input

How did you get to know about this programme?(*)
Invalid Input

Terms and Conditions
Invalid Input

Invalid Input