PCIe Protocol Overview

This 1 day course focuses on the fundamentals of the PCI Express protocol specification. The typical PCIe architecture, including data space, data movement, and the most commonly used Transaction Layer Packets (TLPs) are covered, interrupts and error handling are also discussed.

Implementattion issues are covered in the two-day Designing an integrated PCI Express System course.

Software Tools

  • None required
  • VCD viewer optional

Hardware

  • Architecture: N/A*
  • Demo board; None*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Interpret various transactions occuring on the link
  • Describe the layered architecture and tasks and packet types each is responsible for
  • Properly estimate maximum performance of a link
  • Illustrate how errors can be communicated within the system
  • Explain the relationship between Virtual Channels (VCs) and Traffic Class (TC) and the interaction with flow contro credits

 

Course Outline

Day 1

1.1 Introduction

1.2 Introduction to the PCIe Architecture

1.3 Review of the PCIe Protocol

1.4 Packet Formatting Details

1.5 Lab 1: Packet Decoding

This lab explores what really happens on the link between a root complex and the endpoint. Various packets, including the Phyical Layer, Data Link Layer, and Transaction Layer packets are explored.

Insight as to what is actually transpiring on the lanes becomes a powerful tool for understanding the protocol as well as debugging various link issues.

1.6 Packet Routing

1.7 Interrupts and Error Management

1.8 Summary

 

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