Designing with Xilinx Serial Transceivers

Course Description

In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.

Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.

Training Duration

2 days

Who Should Attend?

FPGA designers and logic designers

Prerequisites

  • Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
  • Familiarity with logic design (state machines and synchronous design)
  • Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

  • Vivado® System Edition 2016.3
  • Mentor Graphics Questa Advanced Simulator 10.4

Hardware

  • Architecture: 7 series and UltraScale FPGAs*
  • Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
  • Effectively utilize the following features of the gigabit transceivers:
    • 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
    • Pre-emphasis and receive equalization
  • Use the Transceivers Wizards to instantiate GT primitives in a design
  • Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
  • Use the IBERT design to verify transceiver links on real hardware

 

Course Outline 

Day 1

1.1 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview

1.2 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets

1.3 Transceiver IP Generation – Transceiver Wizard

1.4 Lab 1: Transceiver Core Generation

Use the Transceivers Wizard to create instantiation templates.

1.5 Transceiver Simulation

1.6 Lab 2: Transceiver Simulation

Simulate the transceiver IP by using the IP example design.

1.7 PCS Layer General Functionality

1.8 PCS Layer Encoding

1.9 Lab 3: 64B/66B Encoding

Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.

Day 2

2.1 Transceiver Implementation

2.2 Lab 4: Transceiver Implementation

Implement the transceiver IP by using the IP example design.

2.3 PMA Layer Details

2.4 PMA Layer Optimization

2.5 Lab 5: IBERT Design

Verify transceiver links on real hardware.

2.6 Transceiver Test and Debugging

2.7 Lab 6: Transceiver Debugging

Debug transceiver links.

2.8 Transceiver Board Design Considerations

2.9 Transceiver Application Examples

 

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