DSP Design Using System Generator

This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities.

Level

DSP 3 

Training Duration

2 days

Who Should Attend?

System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design

Prerequisites

  • Experience with the MATLAB and Simulink software 

  • Basic understanding of sampling theory

Software Tools

  • Vivado® System Edition 2016.3

  • MATLAB with Simulink software R2016b

Hardware

  • Architecture: 7 series FPGAs*

  • Demo board: Kintex®-7 FPGA KC705 board and Zynq®-7000 All Programmable Soc ZC702 or ZedBoard

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the System Generator design flow for implementing DSP functions 
  • Identify Xilinx FPGA capabilities and implement a design from algorithm concept to hardware simulation
  • List various low-level and high-level functional blocks available in System Generator
  • Run hardware co-simulation
  • Identify the high-level blocks available for FIR and FFT designs
  • Implement multi-rate systems in System Generator
  • Integrate System Generator models into the Vivado IDE
  • Design a processor-controllable interface using System Generator for DSP
  • Generate IPs from C-based design sources for use in the System Generator environment

Course Outline

Day 1

1.1 Introduction to System Generator
1.2 Simulink Software Basics
1.3 Lab 1: Using the Simulink Software
Learn how to use the toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.
1.4 Basic Xilinx Design Capture
1.5 Demo: System Generator Gateway Blocks
1.6 Lab 2: Getting Started with Xilinx System Generator
Illustrates a DSP48-based design. Perform hardware co-simulation verification targeting a Xilinx evaluation board.
1.7 Signal Routing
1.8 Lab 3: Signal Routing
Design padding and unpadding logic by using signal routing blocks.
1.9 Implementing System Control
1.10 Lab 4: Implementing System Control
Design an address generator circuit by using blocks and Mcode.

Day 2

2.1 Multi-Rate Systems
2.2 Lab 5: Designing a MAC-Based FIR
Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using a Xilinx evaluation board.  
2.3 Filter Design
2.4 Lab 6: Designing a FIR Filter Using the FIR Compiler Block
Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using a Xilinx evaluation board.
2.5 System Generator, Vivado Design Suite, and Vivado HLS Integration
2.6 Lab 7: System Generator and Vivado IDE Integration
Embed System Generator models into the Vivado IDE.
2.7 Kintex-7 FPGA DSP Platforms
2.8 Lab 8: System Generator and Vivado HLS Tool Integration
Generate IP from a C-based design to use with System Generator.
2.9 Lab 9: AXI4-Lite Interface Synthesis
Package a System Generator for DSP design with an AXI4-Lite interface and integrate this packaged IP into a Zynq All Programmable SoC processor system.

 

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