SDSoC Adopter Class

Course Description 

Combines Vivado HLS and SDSoC Development Environment & Methodology

This 3 day combination training course provides the project-ready skills necessary to exploit the SDSoC Development Environment to create accelerated systems.

It combines training on Vivado HLS with a practical workshop using the SDSoC environment itself.

Training Duration

3 days

Who Should Attend?

Anyone interested in quickly adding hardware acceleration to a software system.

Software and hardware engineers looking to utilize high-level synthesis

Prerequisite 
  • C, C++, or System C knowledge
  • High-level synthesis for software engineers OR high-level synthesis for hardware engineers
  • Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
  • Comfort with the C programming language
  • Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
Software Tools
  • Vivado System Edition 2017.3
  • SDXTm development environment
Hardware
  • Architecture: Zynq-7000 All Programmable SoC*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*
Skills Gained

After completing this comprehensive training, you will know how to:

  • Enhance productivity by using Vivado HLS (high-level synthesis)
  • Describe the high-level synthesis flow
  • Use Vivado HLS for a first project
  • Identify the importance of the testbench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of IP generated by Vivado HLS
  • Describe how to use OpenCV functions in the Vivado HLS tool
  • Identify candidate functions for hardware acceleration by using the TCF profiling tool
  • Use the System Debugger's capabilities to control the execution flow and examine memory and variables during a debug session
  • Move designated software functions to hardware and estimate the performance of the accelerator and the effect on the entire system
  • Use the hardware/software event to understand the performance of an application given the workload, hardware/ software partitioning, and system design choices.
Course Outline 

 

Day 1

1.1 Introduction to High-Level Synthesis

Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage.

1.2 Basics of the Vivado HLS Tool

Explore the basics of high-level synthesis and the Vivado HLS tool.

1.3 Design Exploration with Directives

Explore different optimization techniques that can improve the design performance.

1.4 Vivado HLS Tool Command Line Interface

Describes the Vivado HLS tool flow in command prompt mode.

1.5 Introduction to HLS UltraFast Design Methodology

Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps.

1.6 Introduction to I/O Interfaces

Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design.

1.7 Block-Level Protocols

Explains the different types of block-level protocols abstracted by the Vivado HLS tool.

1.8 Port-Level Protocols

Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design.

1.9 Port-Level Protocols: AXI4 Interfaces

Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave) and AXI4-Stream) supported by the Vivado HLS tool.

1.10 Port-Level Protocols: Memory Interfaces

Describes the Memory Interface port-level protocols (such as BRAM, FIFO) abstracted by the Vivado HLS tool from the C design.

1.11 Port-Level Protocols: Bus Protocol

Explains the bus protocol supported by the Vivado HLS tool.

1.12 Pipeline for Performance: PIPELINE

Describes the PIPELINE directive for improving the throughput of a design.


Day 2

2.1 Pipeline for Performance: DATAFLOW

Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to executes as soon as possible.

2.2 Optimizing Structures for Performance

Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.

2.3 Data Pack and Data Dependencies

Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design.

2.4 Vivado HLS Tool Default Behavior: Latency

Describes the default behavior of the Vivado HLS tool on latency and throughput.

2.5 Reduce Latency

Describes how to optimize the C design to improve latency.

2.6 Improving Area

Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.

2.7 Introduction to HLx Design Flow

Describes the traditional RTL flow versus the Vivado HLx design flow.

2.8 HLS vs. SDSoC Development Environment Flow

Describes the HLS flow versus the SDSoC™ development environment flow.

2.9 Vivado HLS Tool: C Code

Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types.

2.10 Hardware Modeling

Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.

2.11 OpenCV Libraries

Explains the OpenCV design flow and the Vivado HLS tool support.

2.12 Pointers

Explains the use of pointers in the design and workarounds for some of the limitations.


Day 3

3.1 Zynq AP SoC Architecture Support for Accelerators   [Optional]

Discusses the relevant aspects of the Zynq All Programmable SoC architecture for accelerator design. The focus is on AXI ports and protocols, system latency, and memory utilization.

3.2 Software Overview [Optional]

Provides a thorough understanding of how the integrated design environment works, including how the compiler and linker behave, basics of makefiles, DMA usage, and variable scope.

3.3 Introduction to the SDSoC Tool

Introduces the purpose, underlying structures, and basic functionality of the SDSoC development environment.

3.4 SDSoC Tool Flow

Explains the complete development flow of the SDSoC integrated development environment (IDE).  

3.5 Application Debugging

Through the use of the System Debugger, students will learn how to follow the control flow in an executing application and see the effects of the code on memory to successfully debug software issues.  

3.6 Application Profiling

Profiling is the process that identifies how the processor is spending its time. Through profiling, the user can quickly identify which functions must be optimized or moved to hardware to satisfy the performance requirements.  

3.7 Understanding Estimations in the SDSoC Tool

Once a function is moved to hardware, questions remain: Will the accelerator fit in hardware? Will it fun fast enough? Estimations can provide the answers.  

3.8 QEMU Emulation

Describes how to use the emulation feature in the SDx IDE.

3.9 Hardware/Software Event Tracing

Hardware/software event tracing helps users understand the performance of their application given the workload, hardware/software partitioning, and system design choices. Such information helps the user to optimize and improve system implementation

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