C-based Design: High-Level Synthesis with the Vivado HLS Tool

The course provides a thorough introduction to the Vivado® High-Level Synthesis (HLS) tool. This course covers synthesis strategies, features, improving throughput, area, interface creation, latency, testbench coding, and coding tips. Utilize the Vivado HLS tool to optimize code for high-speed performance in an embedded environment and download for in-circuit validation.

Level

DSP 3 

Training Duration

2 days

Who Should Attend?

Software and hardware engineers looking to utilize high-level synthesis

Prerequisites

  • C, C++, or System C knowledge

  • High-level synthesis for software engineers OR high-level synthesis for hardware engineers

Software Tools

  • Vivado System Edition 2016.3
  • SDSoC™ development environment 2016.3

Hardware

  • Architecture: Zynq®-7000 All Programmable SoC and 7 series FPGAs*

  • Demo board: Zynq-7000 All Programmable SoC ZC702 or Zed board*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Enhance productivity by using the Vivado HLS tool
  • Describe the high-level synthesis flow
  • Use the Vivado tool HLS for a first project
  • Identify the importance of the testbench
  • Use directives to improve performance and area and select RTL interfaces
  • Identify common coding pitfalls as well as methods for improving code for RTL/hardware
  • Perform system-level integration of IP generated by the Vivado HLS tool
  • Describe how to use OpenCV functions in the Vivado HLS tool

Course Outline 

Day 1

1.1 Introduction to High-Level Synthesis

      Overview of the High-level Synthesis (HLS), Vivado HLS tool flow, and the verification advantage.

1.2 Basics of the Vivado HLS Tool

      Explore the basics of high-level synthesis and the Vivado HLS tool.

1.3 Design Exploration with Directives

       Explore different optimization techniques that can improve the design performance.

1.4 Vivado HLS Tool Command Line Interface

       Describes the Vivado HLS tool flow in command prompt mode.

1.5 Introduction to HLS UltraFast Design Methodology

      Introduces the methodology guidelines covered in this course and the HLS UltraFast Design Methodology steps

1.6 Introduction to I/O Interfaces

      Explains interfaces such as block-level and port-level protocols abstracted by the Vivado HLS tool from the C design.

 1.7 Block-Level Protocols

       Explains the different types of block-level protocols abstracted by the Vivado HLS tool.

 1.8 Port-Level Protocols 

      Describes the port-level interface protocols abstracted by the Vivado HLS tool from the C design.

 1.9 Port-Level Protocols: AXI4 Interfaces

      Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite(Slave) and AXI4-Stream) supported by the Vivado HLS tool.

 1.10 Port-Level Protocols: Memory Interfaces

       Describes the Memory Interface port-level protocols (such as BRAM, FIFO) abstracted by the Vivado HLS tool from the C design.

1.11 Port-Level Protocols: Bus Protocol

        Explains the bus protocol supported by the Vivado HLS tool.

 1.12 Pipeline for Performance: PIPELINE

        Describes the PIPELINE directive for improving the throughput of a design.

Day 2

2.1 Pipeline for Performance: DATAFLOW

      Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible.

2.2 Optimizing Structures for Performance

      Learn the performance limitations caused by arrays in your design, You will also learn some optimization techniques to handle arrays for improving performance.

2.3 Data Pack and Data Dependencies

       Learn how to use DATA_PACK and DEPENDENCE directives to overcome the limitations caused by structures and loops in the design.

2.4 Vivado HLS Tool Default Behavior: Latency

       Describes the default behavior of the Vivado HLS tool on latency and throughput.

2.5 Reduce Latency

      Describes how to optimize the C design to improve latency.

2.6 Improving Area

      Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization.

2.7 Introduction to HLx Design Flow

       Describes the traditional RTL flow versus the Vivado HLx design flow.

2.8 HLS vs. SDSoC Development Environment Flow 

      Describes the HLS flow versus the SDSoCTM development environment flow.

2.9 Vivado HLS Tool: C Code

      Describes the Vivado HLS tool support for the C/C++ languages, as well as arbitrary precision data types.

2.10 Hardware Modeling

       Explains hardware modeling with streaming data types and shift register implementation using the ap_shift_reg class.

2.11 OpenCV Libraries

        Explains the OpenCV design flow and the Vivado HLS tool support.

2.12 Pointers

        Explains the use of pointers in the design and workarounds for some of the limitations.

 

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