Advanced SDSoC Development Environment and Methodology

Course Description
This two-day course is structured to help designers employ SDSoC™ development environment optimization techniques to create high-performance, accelerated systems. The focus is on optimizing memory access and hardware functions, generating C-callable IP libraries, and creating custom platforms. The course also includes an introduction to the Xilinx reVISION Stack.

Training Duration
2 Days

Who Should Attend?
Anyone interested in implementing SDSoC development environment optimization techniques.

Prerequisites
Understanding of Zynq®-7000 architecture (with emphasis on ACP, HP ports, and internal routing)
Comfort with the C programming language
Familiarity with the Vivado® Design Suite, Vivado HLS tool, and Xilinx SDK
SDSoC Development Environment and Methodology course

Software Tools
SDx™ development environment 2017.1

Hardware
Architecture: Zynq-7000 All Programmable SoC*
Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard*

Skills Gained
After completing this comprehensive training, you will know how to:

Improve the memory accesses and data transfer rate between the PS and PL (macro-architecture optimization)
Apply HLS directives to enhance the performance of hardware functions (micro-architecture optimization)
Create a C-callable library for IP blocks written in a hardware description language like VHDL or Verilog
Override tool defaults to improve the performance of individual accelerators and the overall system
Create a custom platform using the SDSoC Platform Utility (sdspfm)
Describe how the reVISION Stack enables users to quickly develop applications based on machine learning and computer vision with the SDx development environment

Course Outline

Day 1

1.1 SDSoC Environment Optimization
Describes different optimization techniques in the SDSoC development environment, such as macro-architecture and micro-architecture optimizations.

1.2 Memory Access Optimization
Describes how to improve the memory access and the data transfer rate between the PS and PL.

1.3 Blocking and Non-Blocking Implementations in the SDSoC Tool
Addresses how the processor behaves while the accelerator is producing solutions—does it wait or continue on?

1.4 Implementing Multiple Accelerators in the SDSoC Tool
There are times when moving a single function to hardware is not enough—multiple functions must be moved to hardware, or one accelerator must be duplicated. Here students will learn to control how the tool produces the accelerators.

1.5 Basics of the Vivado HLS Tool
Explore the basics of high-level synthesis and the Vivado HLS tool.

1.6 Design Exploration with Directives (Pragmas)
Explore different optimization techniques that can improve the design performance.

1.7 Pipeline for Performance: PIPELINE
Describes the PIPELINE directive for improving the throughput of a design.

1.8 Pipeline for Performance: DATAFLOW
Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible.

Day 2

2.1 Optimizing Structures for Performance
Learn the performance limitations caused by arrays in your design. You will also learn some optimization techniques to handle arrays for improving performance.

2.2 C-Callable IP Library
Describes how to create a C-callable library for IP blocks written in a hardware description language like VHDL or Verilog.

2.3 SDSoC Platform Creation
Describes how to create a custom SDSoC platform starting from a hardware system built using the Vivado Design Suite, and a software run-time environment, including an operating system kernel, boot loaders, file system, and libraries.

2.4 Optimizing the Design
Apply all the techniques you have learned to meet the performance goal for a given design.

2.5 reVISION Stack
Describes the Xilinx reVISION Stack and how it enables application developers to quickly develop applications based on machine learning or computer vision using the SDx development environment.

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