Debugging Techniques Using the Vivado Logic Analyzer

Course Description

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use Vivado® logic analyzer debug solution helps minimize the amount of time required for verification and debug.

This one-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the Vivado debug tool can address advanced verification and debugging challenges.

Release Date

June 2015

Level

FPGA 2

Training Duration

1 day

Who Should Attend

System and logic designers who want to minimize verification and debug time.

Prerequisites

Software Tools

  • Vivado Design or System System Edition

Hardware

  • Architecture: N/A*
  • Demo board: Kintex®-7 FPGA KC705 board*

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Identify each Vivado IDE debug core and explain its purpose
  • Effectively utilize the Vivado logic analyzer
  • Implement the Vivado IDE debug cores using both the netlist insertion and HDL instantiation tool flows
  • Select effective test points in your design
  • Optimize design and core performance when debug cores are used
  • Execute various techniques for collecting data including
    • File storage
    • Scripting
    • Building custom triggers

Course Outline

  • How the Vivado Logic Analyzer Works
  • Adding the Debug Cores – Netlist Insertion Flow
  • Lab 1: Inserting a Debug Core Using the Netlist Insertion Flow
  • Instantiating the Debug Cores – HDL Instantiation Flow
  • Lab 2: Adding a Debug Core Using the HDL Instantiation Flow
  • Debug Flow in IP Integrator
  • Lab 3: Debugging Flow – IPI Block Design
  • Triggering and Visualizing Data
  • Tips and Tricks
  • Lab 4: Tips and Tricks
  • Scripting
  • Lab 5: VIO Tcl Scripting
  • Remote Access
  • Lab 6: Remote Access

* Check with your Authorized Training Provider to confirm whether this content is included with your specific class.

Lab Descriptions

  • Lab 1: Inserting a Debug Core Using the Netlist Insertion Flow – Insert ILA cores into an existing synthesized netlist and debug a common problem.
  • Lab 2: Adding a Debug Core Using the HDL Instantiation flow – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.
  • Lab 3: Debugging Flow – IPI Block Design – Add an ILA IP core to a provided block design and connect nets to the core. Observe its behavior using the Vivado logic analyzer.
  • Lab 4: Tips and Tricks – Sample across multiple time domains and use advanced trigger and capture capabilities.
  • Lab 5: VIO Tcl Scripting – Configure automated analysis.
  • Lab 6: Remote Access – Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location

DOWNLOAD REGISTRATION FORM

  ONLINE REGISTRATION

 

Course Registration Form


Course Title
Invalid Input

or Key in Your Own Title
Invalid Input

Course Start Date

Invalid Input

Sponsorship (*)
Invalid Input


Contact Person


Salutation(*)
Invalid Input

Name(*)
Invalid Input

Designation/ Department/ Division(*)
Invalid Input

Company(*)
Invalid Input

Billing Address (*)
Invalid Input

Street Address

(*)
Invalid Input

Street Address Line 2

City(*)
Invalid Input

State / Province(*)
Invalid Input

Postal / Zip Code(*)
Invalid Input

Telephone(*)
Invalid Input

Fax
Invalid Input

Email Address (*)
Invalid Input


Participant Details


Participant Salution 1
Invalid Input

Participant Name1
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 2
Invalid Input

Participant Name2
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Participant Salution 3
Invalid Input

Participant Name 3
Invalid Input

Designation/ Department/ Division
Invalid Input

Telephone
Invalid Input

Fax
Invalid Input

Email Address
Invalid Input

Dietary Requirement
Invalid Input


Payment Method(*)
Invalid Input

Cheque number
Invalid Input

PO Number
Invalid Input

How did you get to know about this programme?(*)
Invalid Input

Terms and Conditions
Invalid Input

Invalid Input