Designing with Verilog

This comprehensive course is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This course covers Verilog 1995 and 2001.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no Verilog knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Training Duration

3 days

Who Should Attend?

Engineers who want to use Verilog effectively for modeling, design, and synthesis of digital designs

Prerequisites

  • Basic digital design knowledge

Software Tools

  • Vivado® Design or System Edition 2016.3

Hardware

  •    Architecture: N/A*
  •    Demo board: Kintex®-7 FPGA KC705 board*

Skills Gained

After completing this comprehensive training, you will know how to:

  • Write RTL Verilog code for synthesis
  • Write Verilog test fixtures for simulation
  • Create a Finite State Machine (FSM) by using Verilog
  • Target and optimize Xilinx FPGAs by using Verilog
  • Use enhanced Verilog file I/O capability
  • Run a timing simulation by using Xilinx Simprim libraries
  • Create and manage designs within the Vivado Design Suite environment
  • Download to the evaluation demo board 

Course Outline 

Day 1

1.1 Introduction to Verilog

1.2 Verilog Keywords and Identifiers

1.3 Verilog Data Types

1.4 Verilog Buses and Arrays

1.5 Verilog Modules and Ports

1.6 Demo: Multiplexer

1.7 Lab 1: Building Hierarchy

1.8 Verilog Operators

1.9 Continuous Assignment

1.10 Gate-Level Modeling

1.11 Procedural Assignment

1.12 Blocking and Non-Blocking Procedural Assignment

1.13 Lab 2: Creating a Simple Memory

1.14 Procedural Timing Control


Day 2

2.1 Verilog Conditional Statements: if_else

2.2 Lab 3: Building the Clock Divider and Address Counter

2.3 Verilog Conditional Statements: case

2.4 Verilog Loop Statements

2.5 Introduction to Verilog Testbenches

2.6 Lab 4: Verilog Simulation and RTL Verification

2.7 System Tasks

2.8 Verilog Sub-Programs

2.9 Verilog Functions

2.10 Verilog Tasks

2.11 Verilog Compiler Directives

2.12 Parameter Concept

2.13 Lab 5: Creating an n-bit Binary Counter

2.14 Generate Statement

Day 3

3.1 Verilog Timing Checks

3.2 Finite State Machine

3.3 Finite State Machine: Mealy

3.4 Lab 6: Building a Mealy Finite State Machine

3.5 Finite State Machine: Moore

3.6 Lab 7: Building a Moore Finite State Machine

3.7 FSM Coding Guidelines

3.8 File I/O Introduction

3.9 File I/O Read Functions

3.10 Lab 8: Using Verilog File I/O

3.11 File I/O Write Functions

3.12 Targeting Xilinx FPGAs

3.13 Lab 9: Implementing and Downloading the Design

3.14 User-Defined Primitives

3.15 Programming Language Interface

 

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