UltraScale and UltraScale+ Architectures Workshop

This is a one-day version of the Designing with the UltraScale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family.

Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered.

In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.


Training Duration
1 Day

Who Should Attend?
Anyone who would like to build a design for the UltraScale™ or UltraScale+™ device family

Prequisities
•Designing FPGAs Using the Vivado Design Suite 1 course
•Intermediate VHDL or Verilog knowledge

Software Tools
•Vivado Design or System Edition 2016.3

Hardware
•Architecture: UltraScale and UltraScale+ FPGAs*
•Demo board: None*

Skill Gained

After completing this comprehensive training, you will have the necessary skills to:


•Take advantage of the primary UltraScale architecture resources
•Define the block RAM and FIFO resources available for UltraScale FPGAs
•Describe the UltraRAM features
•Properly design for the I/O and SERDES resources
•Identify the MMCM, PLL, and clock routing resources included with the UltraScale architecture
•Identify the hard IP resources available for implementing high-performance DDR4 physical layer interfaces
•Describe the additional features of the dedicated transceivers
•Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

1.1 UltraScale Architecture Clocking Resources
Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.

1.2 UltraScale Architecture Block Memory Resources
Review the block RAM resources in the UltraScale architecture.
 
1.3 UltraScale Architecture FIFO Memory Resources
Review the FIFO resources in the UltraScale architecture.
 
1.4 UltraRAM Memory
Use UltraRAM for a design requiring a larger memory size than block RAM.
 
1.5 DDR4 Design Creation Using MIG
Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.
 
1.6 UltraScale Architecture I/O Resources – Component Mode
Implement a high-performance, source-synchronous interface using I/O resources in Component mode for the UltraScale architecture.
 
1.7 UltraScale Architecture I/O Resources – Native Mode
Implement a high-performance, source-synchronous interface using I/O resources in Native mode for the UltraScale architecture.
 
1.8 FPGA Design Migration
Migrate an existing 7 series design to the UltraScale architecture.
 
1.9 UltraScale Architecture Transceivers
Review the enhanced features of the transceivers in the UltraScale architecture.
 
1.10 UltraScale FPGAs Transceivers Wizard
Use the Transceivers Wizard to build a design that uses a single serial transceiver and observe the created file structures.

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